The increasing of higher level of integration within electrical integrated circuit (IC) leads to both higher data rates and larger number of IC interconnections. Today, the inherent signal speed of IC is increased to 3 GHz, and shortly it will be reached to 10 GHz and beyond. The number of pin connection is also increased, with single IC requiring close to 2000 interconnection (i.e. single processor), and shortly it will be increased to over 5000. Simultaneously achieving higher data rates and higher interconnect densities for both on-chip and also off-chip, will be increasingly difficult as the IC technologies continue to evolve increasing signal speed of electronic devices and interconnection number. In on-chip cases (intra chip), as the number of the electronic devices such as transistor are increasing with development of the fabrication technology, the interconnecting the electronic devices without sacrificing the signal speed is getting challenging. In off-chip case, high density interconnects, covering from die-level packaging to chip-to-chip (hereafter chip indicates the die with package) interconnection on the printed circuit board (PCB), will also be getting increasingly difficult as the IC technologies continue to evolve increasing the signal speed and interconnection number.
With increasing of the signal speed and interconnection number within and outside of the IC, low-cost high-level interconnect technique compatible to today's manufacturing process are highly desirable to make available in consumer level.
Generally, it is known that if the electronic devices (for both on-chip and off-chip) are connected with the help of the metal conductor, electrical signal can be flown and the electronic device can be communicated with each other. This is true for the low-speed signal, below few MHz. In high-speed interconnection for both on-chip and off-chip interconnects, all connected signals should be considered to be propagated through well impedance matched transmission line. Any discontinuities in the electrical signal line due to impedance impedance mismatch, or the VIA etc. cause the reflection, which degrades the signal waveform reaching to the other side of the electronics devices. At multi GHz frequencies, interconnect lengths become a significant fraction of the wavelength of the high frequency harmonics, and therefore interconnects must be design with proper concern of impedance, cross talk, and attenuation. Impedance mismatch must be minimized to reduce the reflections and prevent ringing, which can cause false decision (switching) in the receiver signal. Significant attenuation and rise-time degradation can be caused by losses in the transmission line. The transmission line loss is the sum of the conductor loss and dielectric loss, both of which are dependent on the frequency.
Today technology development pushes to reduce the size of the electronic device, resulting in utilization of number of the devices inside single chip. As the level of integration targeting for future ‘system-on-a-chip’ design, is increasing, the chip area is also increasing. Novel interconnection technique compatible to standard IC fabrication technology is necessary; yet preserve the signal speed while assuring the adequate isolation for high-speed data communication. With increasing of intrachip signal speed, the interchip (off-chip) signal speed also increases, which require also novel technique, which could be also compatible to today's PCB technology.
FIG. 1 and FIG. 2 are the schematic showing part of conventional on-chip (intra) and off-chip (inter-chip) interconnections. In on-chip interconnection as shown in FIG. 1, single substrate 100 comprises with many electronics devices 102, and are connected by the metal conductor 104. Dielectric layer 106 such as silicon oxide for Si device isolates each device. Metal conductor such as Al, Cu, W, and WSi etc. is used for connecting on-chip devices.
In off-chip interconnection, as shown in FIG. 2, the chip 120 (for example processor) is connected with chip 130 (for example 3) by multilayered electrical signal lines 110 in the PCB 105. FIGS. 3 and 4 show the schematic representing the conventional BGA (ball grid array) and CSP (chip-scaled package) based packaging for high-speed single chip package (for example processor). In both type of packaging, die 122 and die 132 are attached with the ceramic or polymer substrate 124 and 134, respectively, containing the matrix of pins 126 and 136. Outside pins 128 and 138, located at the bottom-side of chip package (in both packaging cases) connect with the PCB, whereas topside of the package is connected with the heat sink to dissipate heat from the die. Both types of packages provide closer proximity of signal as on-chip. The fidelity of signal occurred due to the conventional interchip electrical signal connections 110 and ground/power 112 through multiplayer PCB 108. It is highly desirable having the board-level electrical interconnects for high-speed interchip connection, which could be compatible with existing IC package such as BGA, CSP etc., and also could be employed conventional PCB technologies.
Today's interconnection technology for both on-chip (intra-chip) and off-chip (inter-chip) are mainly based on the microstrip line or strip-line transmission layout on the dielectric material. FIG. 5A shows a cross-sectional of a microstrip layout, which refers to a trace routed as the top or bottom layer for example of a PCB for the case of off-chip interconnection. The electrical conductor 140A with width W and thickness T are laid on the dielectric material 142A having height H. The ground or power line 144A is located opposite of the signal conductor 140A. FIG. 5B is the cross-sectional view of strip line layout, which uses a trace 140B routed on the inside layer 142B for example of a PCB and has two voltage-reference planes (i.e. power and/or ground) 144B and 144B′. The impedances of microstrip line and strip line are expressed by:Zmicrostrip=[(87/Sqrt.(∈r+1.41)]In[(5.98×H)/(0.8W+T)]Ω  (1)Zstrip=[(60/Sqrt.(∈r))]]]In[(4H)/(0.67 π(0.8W+T))]]]Ω  (2)
Equations (1) and (2) indicate that the impedance is directly proportional to the dielectric constant ∈r, trace height H, and the inversely proportional to the trace width W and trace thickness T. In stripline layout, the signal line is sandwiched by the dielectric layer, whereas a microstrip layout has one conductor open to air. In microstripline type traces, the field is in both dielectric layer and air whereas in strip line type traces, the filed is confined inside dielectric materials. This causes a higher, effective dielectric constant stripline layout compared to microstrip layouts. Besides, these also causes the less dielectric loss in microstripline as compared with stripline. Higher effective dielectric loss experiences much dispersion or signal loss as compared with that of the microstrip line layout. FIG. 6 shows the top view and cross-sectional view of the microstrip line transmission layout, showing the electrical field distribution. The electrical field 146A is spreading both side of the electrical signal line 140A. FIGS. 7A and 7B are the frequency response of the microstrip line and strip line layout. As the effective dielectric constant (using of the same material) of the strip line layout is higher than that of the microstrip line layout. The signal is attenuated more in strip line layout in compared with increasing of the frequency. This also suggests that effective dielectric loss should be kept low to increase the bandwidth of the interconnection.
High-speed signal while propagating through the transmission line experiences the signal propagation delay, and it is dependent on the dielectric constant of the material. The signal propagation delay for the strip line and microstrip lines are expressed by:tPD microstrip=85[Sqrt.(0.475∈r+0.67)]  (3)tPD strip=85[Sqrt.(∈r)]  (4)
Equations (3) and (4) indicate that as ∈r increases, the propagation delay also increases. Microstrip line has comparatively lower propagation delay than the strip line layout for the fixed dielectric constant ∈r.
As mentioned earlier, electrical field inside dielectric material having higher dielectric constant experiences more signal delay as compared with that of transmission line comprising with lower dielectric constant material. These causes signal skews for the different length signal lines. In this case also, lower dielectric constant material is necessary in the interconnection for high-speed signal interconnection. This is true for both on-chip and off-chip interconnection. Lower dielectric constant material with low dielectric loss offers following functions;
(1) Higher density interconnection is possible due to reduction of the cross-talk;
(2) reducing the capacitance of the interconnection, helping to transfer the signal longer distance;
(3) lower propagation delay; and
(4) reducing the microwave loss as the field is spread closer to the electrical conductor, and help to transmit the longer distance. In other words, help to transmit the higher speed signal as compared with the higher dielectric constant and with same loss tangent.
Besides the dielectric constant of the material or the type of the signal line, the microwave loss due to dielectric material and also the electrode structure also limits the bandwidth of the interconnection. Microwave-loss occurs due to the electrode structure mainly from skin-depth of the signal. As Cu's skin-depth at 100 GHz is 0.2 μm, the skin-depth due to the conductor structure is neglected. So, the bandwidth of the interconnection (for both on-chip and off-chip interconnection) is mainly dependent on the following factors:
(1) length of the interconnects; and
(2) microwave-loss, mainly originated from the (a) dielectric constant, (b) dielectric loss tangent, and (c) electrode structure.
As the length of the interconnections in on-chip and off-chip varies from the few micrometers to 10 to 30 cm, the length dependency can be neglected. Mainly, the interconnection bandwidth is dependent on the dielectric constant and the material loss tangent.
It is very straight forward that increasing the bandwidth can be possible using of the material having the lower loss tangent (dielectric loss). However, in this case, for both on-chip and off-chip interconnection new material development is necessary. Additionally, manufacturing technology development is needed to implement product-level devices.
Much work can be found in both on-chip and off-chip interconnection technology focusing on the material development. As for example, in on-chip interconnection, low-K (dielectric constant) material is under development stage, to achieve lower dielectric constant than non-doped silicon oxide. Lowering the dielectric constant than silicon oxide is possible in some extend from material characteristic point view, which is not long-term technique, and beyond that different materials are necessary. Besides, implementing new material in chip fabrication process will cost tremendously to make it mature. Having low-K material for on-chip interconnection is not only time consuming development, but also the costly short-term solution. On the other hands, in off-chip interconnection, especially for the chip-to-chip interconnection, more focused are being paid on shortening the length or on the interconnection layout. In both cases, implementing technology would need to pay high cost.
As explained above, the conventional electronics interconnect technology being used in on-chip and off-chip interconnection cannot be used as the need of the signal speed is increasing. And also exiting conventional electrical interconnects have the limitation of achieving the bandwidth in certain level, beyond that complete manufacturing technology is needed to be changed which is costly for IC and PCB industries. It is highly desirable to have lower dielectric constant and lower dielectric loss (loss tangent) by adopt a technique or method which can be easily implemented, and which can use the standard dielectric material and IC and PCB technology.